(1) Field of the Invention
The present invention relates generally to a structure of and manufacturing process for a semiconductor device which provides improved ESD protection of active semiconductor devices and more particularly to a signal gate ground clamping element for cascaded metal oxide semiconductor (MOS) circuit configuration.
(2) Description of Prior Art
Because of high input impedance and thin oxide gate structures, the problem of Electrostatic Discharge (ESD) damage with field effect transistor (FET) devices can be severe. Therefore the input/output (I/O) circuit locations or pads usually have a protective device connected between the I/O pad and the internal circuits which allows the ESD current to be shunted to ground Another important characteristic of the ESD protection device is that it must not interfere with the operation of the devices it is designed to protect, while at the same time providing good protection when abnormal or ESD voltage incidents occur.
Typical ESD protection devices consist of a N channel metal oxide semiconductor (NMOS) connected to I/O pad A parasitic NPN bipolar device is essentially in parallel with the NMOS device which has a collector base breakdown triggered by the ESD voltage. Once triggered by an ESD incident, the parasitic device operates in a secondary breakdown mode to clamp the ESD voltage to a suitable level and pass the high current to a second voltage source, typically ground.
Integrated logic circuits frequently have a complimentary MOS output string as typified in FIG. 1 utilizing xe2x80x9cusedxe2x80x9d or active devices PMOS PU1, first or cascaded NMOS NU1, second or switched NMOS NU2, and xe2x80x9cunusedxe2x80x9d or xe2x80x9cdummyxe2x80x9d I/O strings represented by devices PMOS PD1, first unused NMOS ND1, and second unused NMOS ND2. In addition to the complimentary PMOS PU1 and NMOS NU2 signal driven switching devices in the active I/O, the xe2x80x9cusedxe2x80x9d logic string shown in FIG. 1 also has a cascaded first NMOS NU1 in series with the switched second active or xe2x80x9cusedxe2x80x9d NMOS NU2. The gate of first NMOS NU1 has its gate tied to Vcc. This cascaded FET NU1 provides flexibility in circuit logic voltage levels while utilizing a specific FET device design.
In addition to the xe2x80x9cusedxe2x80x9d or active I/O string, a xe2x80x9cDummy I/Oxe2x80x9d or inactive device string is shown in FIG. 1. The string is comprised of a PMVOS PD1 with its gate and drain tied too Vcc, and its source tied to the output pad 1 and to the drain of the cascaded firs xe2x80x9cunused or dummy NMOS ND1. The source of the cascaded NMOS ND1 is tied to the lower second xe2x80x9cmusedxe2x80x9d NMOS ND2. The gate and source of NMOS ND2 are tied to ground.
Referring to the xe2x80x9cusedxe2x80x9d device string, a high logic level signal from the internal circuit, typically 3.3 V or 5V, will turn on the second NMOS NU2 in the xe2x80x9cusedxe2x80x9d or active string essentially pulling the output pad 1 voltage down to ground. The same logic signal assures that the PMOS PU1 is turned off preventing any current flow in the string except during the switching transition. Conversely, a low logic signal from die internal circuit will turn on PMOS PU1 and turn off the NMOS NU2 presenting a voltage at or near Vcc at the output pad.
If an ESD event occurs while the second xe2x80x9cusedxe2x80x9d NMOS NU2 is turned on, high current can flow through the device with the potential for device damage. In addition, even with the device in the off state, a phenomenon known as hot carrier gate tunneling may turn the device on during an ESD event The hot carrier gate tunneling is caused by a high voltage such as produced by an ESD event, being placed on the drain of the NMOS NU2. Carriers gain sufficient energy to cause a positive charge or voltage to accumulate on the gate. This hot carrier gate tunneling positive gate voltage could turn the NMOS NU2 device on, again exposing the device to damage from high ESD current This gate action is detrimental to ESD protection, and damage can possibly occur to one or more devices in the string. A device and method is described which greatly enhances the ESD protection capability of the cascaded NMOS device circuitry and limits the possibility of ESD damage to these devices.
The following patents describe ESD protection devices.
U.S. Pat. No. 6,008,974 (Lee et al.) describes a CMOS ESD output protection circuit with a clamping circuit to prevent NMOS damage. The clawing circuit comprises an NMOS transistor, a resistor, and a diode.
U.S. Pat. No. 5,986,867 (Duvvury) discloses an output protection circuit where an NMOS transistor is used as a dummy device.
U.S. Pat. No. 6,091,594 (Williamson et al) shows a CMOS ESD protection circuit where a cascaded NMOS stack is used.
U.S. Pat. No. 6,078,487 (Partovi et al.) shows an ESD circuit with an ESD clamp.
U.S. Pat. No. 6,091,595 (Sharpe Geisler) shows an ESD protection circuit for a 5V output buffer.
U.S. Pat. No. 5,610,790 (Staab et al.), U.S. Pat. No. 6,008,970 (Maloney et al.), and U.S. Pat. No. 5,708,550 (Avery) show related ESD circuits.
Accordingly, it is the primary objective of the invention to provide a novel effective circuit structure, and a circuit development method, for protecting integrated circuits from damage caused by ESD events occurring during circuit operation.
In addition, it is an objective of this invention to provide this ESD protection while maintaining appropriate normal circuit operating parameters of the devices being protected.
It is yet another object of the invention to provide a process method for forming the ESD protection structure that is fully compatible with the manufacturing process of the devices being protected.
The above objectives are achieved in accordance with the embodiments of the invention that describes a process and novel structure for a clamping FET device for the active signal switched NMOS transistor of the complimentary output inverter of CMOS logic devices. A NMOS clamping device has the drain connected to the gate of the output circuit string active switching NMOS that is normally controlled by the signal from the internal circuits. Therefore, the drain of the clamping NMOS device is also connected to the internal circuit signal line. The gate of the clamping device is connected to the output pad through a Pxe2x88x92N diode with the diode negative N side connected to the I/O pad. The NMOS device gate is also connected to a second voltage source, typically ground, through a resistor. The source of the NMOS clamping device is connected directly to ground.
A high voltage from an ESD event causes the diode to operate in reverse breakdown mode thereby conveying a positive voltage to the gate of the clamping device turning it on enabling the active switched NMOS gate to be clamped to ground. Clamping the active NMOS gate to ground prevents the output device from being turned on during the duration of the ESD event by either a logic signal from the internal circuit or the hot carrier effect from the high ESD voltage on the drain. The resistor from the clamping device gate to ground provides the clamping device turn on voltage from the ESD event. The resistor is also in series with the diode, and therefore limits the current generated by the ESD event to protect the diode from damage.
During normal circuit operation the gate of the clamping device is shielded from normal logic signals by the diode, and is essentially grounded through the resistor assuring that the clamping device is in an off state. This prevents any interference with the normal I/O and logic circuit operational characteristics.